Bitlines are conductive lines or traces that may couple a memory cell write driver to a memory cell to be written. Bitlines may capacitively load a write driver and decrease the slew rate of data transmitted over the bitline. The more memory cells are coupled to the write driver, the longer the bitlines may be and the larger the capacitance of the bitline may become.
In dual port memory cells, the conventional use of supply collapse-based write assist techniques result in functional failure. As another example, in single port SRAMs, conventional negative voltage bitline techniques may use a large pull-down transistor to provide a negative voltage supply or ground reference for the write driver. The pull-down transistor used in conventional approaches may be large to ensure that write data slew remains within acceptable limits and the virtual ground voltage of the write driver is close to Vss. However, a large pull-down transistor increases the area of the write driver, thereby consuming valuable silicon real estate.
An additional drawback of conventional approaches to negative voltage bitline techniques is that the designs may not be modular. In other words, modifications to the design to compensate for process variations and/or increases in the number of memory cells (and bitlines) may necessitate post-silicon tuning with programmable capacitors and pass/transmission gates to support programming. These additional components further add to the consumption of silicon real estate while adding additional parasitic resistances.